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SDRAM
120       
NS7520 Hardware Reference, Rev. D 03/2006
SDRAM read cycles
Figure 11 and Figure 12 provide timing examples for SDRAM normal and burst reads,
respectively, with WAIT and BCYC configured with a value of 0.
Figure 11: SDRAM normal read
One Valid Per Cycle
precharge activate read bstop
BCLK
TS_
RW_
BE[3:0]
D[31:0]
CS[7:0]_
CAS3_(RAS_)
CAS2_(CAS_)
CAS1_(WE_)
A[13:0]
AMUX
TA_ {output}
TEA_(LAST_) {output}
TA_ {input}
TEA_(LAST_) {input}