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Chapter 34 CAN Controller
2.Register Description
■ IFx Arbitration Registers (IFxARB)
The bits of the Message Buffer registers mirror the Message Objects in the Message RAM.
MXtd MDir res Msk28-24
⇐ Bit no.
Read/write ⇒
(R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value⇒
(1) (1) (1) (1) (1) (1) (1) (1)
IFx Mask 2 Register high byte
Address : Base + 0x14
H &
Base + 0x44
H
15 14 13 12 11 10 9 8
IFxMSK2H
Msk23-16
⇐ Bit no.
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value⇒
(1) (1) (1) (1) (1) (1) (1) (1)
Address :
Base + 0x
15H &
Base + 0x
45H
765432 10
IFxMSK2L
IFx Mask 2 Register low byte
Msk15-8
⇐ Bit no.
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value⇒
(1) (1) (1) (1) (1) (1) (1) (1)
IFx Mask 1 Register high byte
Address : Base + 0x16
H &
Base + 0x46
H
15 14 13 12 11 10 9 8
IFxMSK1H
Msk7-0
⇐ Bit no.
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value⇒
(1) (1) (1) (1) (1) (1) (1) (1)
Address :
Base + 0x
17H &
Base + 0x
47H
765432 10
IFxMSK1L
IFx Mask 1 Register low byte
MsgVal
Xtd Dir ID28-24
⇐ Bit no.
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value⇒
(0) (0) (0) (0) (0) (0) (0) (0)
IFx Arbitration 2 Register high byte
Address : Base + 0x18
H &
Base + 0x48
H
15 14 13 12 11 10 9 8
IFxARB2H
ID23-16
⇐ Bit no.
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value⇒
(0) (0) (0) (0) (0) (0) (0) (0)
Address :
Base + 0x
19H &
Base + 0x
49H
765432 10
IFxARB2L
IFx Arbitration 2 Register low byte
