HARDWARE DESIGN
HOLD/HLDA.
Hold indicates that another
master
is
requesting control of the local bus.
To be acknowledged,
HOLD
must be in its
active HIGH state.
The processor receiving the
"HOLD"
request
will
issue HLDA (HIGH) at the end of the
current data transfer operation. A data transfer
operation
is
one bus cycle for a byte operation
and two bus cycles for a word operation or
interrupt acknowledge.
Mter
HOLD
is
detected as LOW, the proces-
sor
LOWers HLDA, and when the processor
needs to run another cycle, it will again drive
the local bus and control lines.
NMI. Non-Maskable Interrupt
is
an
edge-
triggered input causing a type 2 interrupt.
A subroutine
is
activated via an interrupt vec-
tor
in system memory.
NMI
is
not maskable
by software.
A transition from a
LOW to HIGH initiates
the interrupt
at
the end of the current instruc-
tion. This input
is
internally synchronized.
READY. The READY signal
is
used to add
wait states to the
8088
machine cycle so that
slow
I/O
or memory devices can be used.
READY
is
a synchronized input generated
by the 8284A in response to the
RDYI/
RDY2 or
AENI/
AEN2 inputs.
TEST. This input synchronizes the
CPU
with
an
external event. When used with the "Wait
for test" instruction, the CPU
is
kept in an
idle state until
TEST
is
driven low by
an
external event.
8088 Bus Timing and Minimum Mode Status
The
8088
CPU
communicates with external
logic through the systems bus. This commun-
ication
is
accomplished by a machine cycle,
in which data
is
tranferred between the
8088
and a memory
or
peripheral device. During
this machine cycle, the
8088
first generates an
3-6
address to select the proper memory or peri-
pheral device. Then the
8088
activates the
read or write control-line, and the data
is
either transferred into the
8088
from the
selected memory or peripheral device (a read
cycle) or
out
of
the
8088
to the selected
memory or peripheral device (a write cycle).
On termination of the cycle, the data
is
latched by the
8088
(read), or the selected
device (write), and the control signal
is
deactivated.
The basic machine cycle of the
8088
consists
of four clock periods or
T-states, TI,
T2,
T3
and T
4.
(Fig. 3-7)
During the first T state (T
I),
the CPU places
an address on the 20-bit address/ datal status
bus. This address specifies a unique location
in the memory or
I/O
address spaces
of
the
iAPX
88,
and
is
guaranteed to be valid on the
address bus when the ALE (Address Latch
Enable) signal makes a HIGH to
LOW tran-
sition.
By
this time, the
IO/M,
SSO and
DT
/ R control and status signals are also
valid.
These signals tell the external logic which
type
of
machine cycle
is
occurring and in
which direction data
will
flow. The signal
IOj
M specifies whether the addressed device
is
in the iAPX 88's
I/O
space or memory
space.
The
DT/R
(Data Transmit/Receive) signal
will be HIGH if data
is
to be transmitted out
of the
CPU
(a write cycle) or LOW if it
is
to
be read into the
CPU (a read cycle).
SSO can be decoded with
IO/M
and
DT/R
to specify other types of machine cycles such
as Interrupt Acknowledge, Halt and Passive.
During state
T2,
the 8088's lower 8 address!
data pins (ADo-AD7) float in preparation
for the data transfer.
Next, the
DEN
and
RD
or
WR control sig-
nals become valid, to enable the data onto
