1995 Mar 07 11
Philips Semiconductors Product specification
I
2
C-bus controlled YUV/RGB switch
TDA8443A
TIMING CHARACTERISTICS
I
2
C-bus load conditions: 4 kΩ pull-up resistor to +5 V; 200 pF capacitor to GND;
all values are referenced to V
IH
= 3 V and V
IL
= 1.5 V; see Fig.4.
Note
1. Timing t
HD;DAT
deviates from the I
2
C-bus specification. After reset has been activated, a delay of 50 µs must occur
before transmission may be resumed.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.
t
BUF
time bus must be free before start 4.7 −µs
t
SU;STA
set-up time for start condition 4.7 −µs
t
HD;STA
hold time for start condition 4.0 −µs
t
LOW
SCL and SDA LOW time 4.7 −µs
t
HIGH
SCL HIGH time 4.0 −µs
t
r
SCL and SDA rise time − 1.0 µs
t
f
SCL and SDA fall time − 0.3 µs
t
SU;DAT
data set-up time (write) 250 − ns
t
HD;DAT
data hold time (write) note 1 1.0 −µs
t
SU;ACK
acknowledge set-up time − 2 µs
t
HD;ACK
acknowledge hold time 0 −µs
t
SU;STO
set-up time for stop condition 4.7 −µs
Fig.4 I
2
C-bus timing diagram.
handbook, full pagewidth
MLD005
SDA
(WRITE)
SCL
t
BUF
t
SU; STA
t
HD; STA
t
LOW
t
f
t
r
t
HD; DAT
t
SU; ACK
t
HD; ACK
t
LOW
t
SU; STO
t
HIGH
t
SU; DAT
