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PRINCIPLES OF OPERATION
2-4. Power-On Reset Circuit
The power-on reset signal initializes all elements so as to protect against possible operating errors at power-on. The signal
is held for approximately 160ms when power comes on. The reset circuit is shown below.
Fig. 2-13 Power-On Reset Circuit
Fig. 2-13 Power-On Reset Circuit
1 At power-on, voltage detector IC3 (M51953BL) outputs a LOW signal from its OUT terminal. The signal is held
for approximately 160ms by the action of capacitor C9 (0.47µF), in accordance with the following relation:
T = 0.34 × C9 (pF) [µs] = 160ms
2 The LOW signal generates reset of the CPU and gate array, and stops operation of the mechanism drive circuitry.
+5V
IC3
CD
C9
GND
+5V
+5V
+5V
VCC
OUT
D1
IC1 : CPU
Drive circuit
RES
RESO
RESET
+
Gate
array
RESET IC
IC4
CPU
+5V