24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
16
AGP Device Status And Command Register DevA:0x04
Default: 0210 0000h Attribute: See below.
AGP Device Revision and Class Code Register DevA:0x08
Default: 0600 00??h Attribute: See below.
AGP Device BIST-Header-Latency-Cache Register DevA:0x0C
Default: 0000 0000h Attribute: Read only.
Bits Description
31 DPE: detected parity error. Read only. This bit is fixed in the low state.
30 SSE: signaled system error. Read; set by hardware; write 1 to clear. 1=A system error was signaled
(both links were flooded with sync packets) as a result of a CRC error (see
DevA:0x[C8:C4][CRCFEN, CRCERR]). Note: this bit is cleared by PWROK reset but not by
RESET#.
29 RMA: received master abort. Read; set by hardware; write 1 to clear. 1=A request (AGP or PCI)
sent to the host bus received a master abort (an NXA error response). Note: this bit is cleared by
PWROK reset but not by RESET#.
28 RTA: received target abort. Read; set by hardware; write 1 to clear. 1=A request (AGP or PCI) sent
to the host bus received a target abort (a non-NXA error response). Note: this bit is cleared by
PWROK reset but not by RESET#.
27:21 Read only. These bits are fixed in their default state.
20 Capabilities pointer. Read only. This bit is fixed in the high state.
19:3 Read only. These bits are fixed in their default state.
2 MASEN: PCI master enable. Read-write. This bit controls no hardware in the IC.
1 MEMEN: memory enable. Read-write. 1=Enables access to the memory space specified by
DevA:0x10. This bit controls no hardware in the IC.
0 IO enable. Read only. This bit is fixed in the low state.
Bits Description
31:8 CLASSCODE. Read; write once. Provides the AGP bridge class code.
7:0 REVISION. Read only.
Bits Description
31:24 BIST. These bits fixed at their default values.
23:16 HEADER. These bits fixed at their default values.
15:8 LATENCY. These bits fixed at their default values.
7:0 CACHE. These bits fixed at their default values.
