24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
9
The SERR# and PERR# signals are not supported on the AGP bridge.
A_GNT#. AGP master grant signal. Output VDD15 Term Low PU High
A_IRDY#. AGP master ready signal. IO VDD15 Term Term PU PU
A_MB8XDET#. This pin is controlled by DevA:0x40[8XDIS]. It
is designed to be connected to the AGP connector to indicate
support for AGP 3.0 signaling.
Output VDD15 Low Low Low Low
A_PAR. AGP parity signal. IO VDD15 Term Term PU Low
A_PCLK. 66 MHz AGP clock. Output VDD33 Func. Func. Func. Func.
A_PLLCLKO. PLL clock output. See section 4.3 for details. Output VDD33 Func. Func. Func. Func.
A_PLLCLKI. PLL clock input. See section 4.3 for details. Input VDD33
A_REFCG. AGP signal reference output. Analog
output
VDD15
A_REFGC. AGP signal reference input. Analog
input
VDD15
A_REQ#. AGP master request signal. Input VDD15 Term Term PU PU
A_RESET#. AGP bus reset signal. This is asserted whenever
RESET# is asserted or when programmed by
DevB:0x3C[SBRST]. Assertion of this pin does not reset any logic
internal to the IC.
Output VDD33 Low High Low High
A_RBF#. AGP read buffer full signal. Input VDD15 Term Term PU PU
A_SBSTB_[P, N]. AGP differential side band address strobe. In
AGP 3.0 signaling mode, A_SBSTB_P is the first strobe and
A_SBSTB_N is the second strobe.
Input VDD15 Term Term _P: PU
_N: PD
_P: PU
_N: PD
A_SBA[7:0]. AGP side band address signals. Input VDD15 Term Term PU PU
A_ST[2:0]. AGP status signals. Output VDD15 Term Low PU Low
A_STOP#. AGP target abort signal. IO VDD15 Term Term PU PU
A_TRDY#. AGP target ready signal. IO VDD15 Term Term PU PU
A_TYPEDET#. AGP IO voltage level type detect. 0=1.5 volts;
1=3.3 volts (not supported by the IC). The state of this pin is
provided in DevA:0x40[TYPEDET]. This pin is also used for test-
mode selection; see section 9. This signal requires an external
pullup resistor to VDD33 on the systemboard.
Input VDD33
A_WBF#. AGP write buffer full signal. Input VDD15 Term Term PU PU
Pin name and description IO cell
type
Power
plane
AGP 3.0
Signaling
AGP 2.0
Signaling
During
reset
After
reset
During
reset
After
reset
