24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
27
Link Frequency Capability 0 Register DevA:0xCC
Default: 0035 0022h. Attribute: See below.
Link Frequency Capability 1 Register DevA:0xD0
Default: 0035 0002h. Attribute: See below.
Link Enumeration Scratchpad Register DevA:0xD4
Default: 0000 0000h. Attribute: See below.
Bits Description
31:16 FREQCAPA: link A frequency capability. Read only. These bits indicate that A side of the tunnel
supports 200, 400, 600, and 800 MHz link frequencies.
15:12 Reserved.
11:8 FREQA: link A frequency. Read-write. Specifies the link side A frequency. Legal values are 0h (200
MHz), 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: this bit is cleared by PWROK reset,
not by RESET#. Note: after this field is updated, the link frequency does not change until either
RESET# is asserted or a link disconnect sequence occurs through LDTSTOP#.
7:0 REVISION. Read only. Revision A of the IC is designed to version 1.02 of the link specification.
Bits Description
31:16 FREQCAPB: link B frequency capability. Read only. These bits indicate that that B side of the
tunnel supports 200, 400, 600, and 800 MHz link frequencies.
15:12 Reserved.
11:8 FREQB: link B frequency. Read-write. Specifies the link side B frequency. Legal values are 0h (200
MHz), and 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: although it is possible to program
this field for higher frequencies, the B link of the IC is only designed to support 200 and 400 MHz
operation. Note: this bit is cleared by PWROK reset, not by RESET#. Note: after this field is updated,
the link frequency does not change until either RESET# is asserted or a link disconnect sequence
occurs through LDTSTOP#.
7:0 Link device feature capability indicator. Read only. These bits are set to indicate that the IC
supports LDTSTOP#.
Bits Description
31:16 Reserved.
15:0 ESP: enumeration scratchpad. Read-write. This field controls no hardware within the IC. Note: this
bit is cleared by PWROK reset, not by RESET#.
