24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
23
AGP Control Register DevA:0xB0
Default: 0000 0000h Attribute: Read-write.
AGP Aperture Size Register DevA:0xB4
Default: 0001 0F00h Attribute: See below.
2:0 DRATE: data transfer mode rate. This field is combined with DevA:0xA4[AGP3MD] to specify
the AGP data rate as follows:
AGP3MD
DRATE
X 000 No AGP mode selected.
0 001 1x AGP rate; AGP 2.0 signaling.
0 010 2x AGP rate; AGP 2.0 signaling.
0 100 4x AGP rate; AGP 2.0 signaling.
1 001 4x AGP rate; AGP 3.0 signaling.
1 010 8x AGP rate; AGP 3.0 signaling.
1100Reserved.
Bits Description
31:10 Reserved.
9 CALDIS: calibration cycle disable. 1=Calibration cycles (as defined in DevA:0xA8[PCALCYC])
are disabled.
8 APEREN: graphics aperture enable. This bit controls no hardware in the IC. It is expected that the
state of this bit is copied into the host by software.
7 GTLBEN: graphics translation look-aside buffer enable. This bit controls no hardware in the IC. It
is expected that the state of this bit is copied into the host by software.
6:0 Reserved.
Bits Description
31:28 PGSZSEL: page size select. Read-write. The only legal value for these bits is 0000b, which specifies
a 4-kilobyte page.
27 Reserved.
26:16 Page size support. Read only. These bits are fixed in their default state to indicate that the IC
supports 4-kilobyte pages.
15:12 Reserved.
